1. Field of the Invention
The present invention relates to a method of testing bit lines of a memory unit, such as an integrated circuit (IC) memory chip, by accessing storage elements of each of a plurality of blocks of the memory unit.
2. Description of the Prior Art
Several proposed methods of testing memory units, such as IC memory chips, are known and include for example, (A) memory scanning, (B) marching, and (C) galloping.
(A) The memory scanning method is a memory unit testing method by which all the bits of data read from the storage elements of the memory unit are tested by sequentially incrementing the address of the memory unit.
(B) The marching method is a similar memory unit testing method. In the marching method, all the bits of data read from the storage elements of a memory unit are tested by sequentially incrementing the address of the memory unit, similarly to the above memory scanning method. In the case of the marching method, initial values, for example, zeros, are written to the memory unit. The zeros are read from and inverted values "ones" are written to the storage elements of the memory unit. This procedure is repeated by sequentially incrementing the memory unit address. It is then detected whether or not all the values finally read from the storage elements of the memory unit are equal to one.
(C) The galloping method is a different memory unit testing method. In the galloping method, it is detected whether or not the binary data read from the storage elements of a memory unit, after the binary data is written to any of the storage elements, interfere with each other. For example, after binary data is written to the storage element at the address 0 of the memory unit, the binary data is read from the storage elements at the addresses 0 and 1 and it is detected whether the interference of the data occurs or not. This is repeated until the combination of the first address 0 and the final address is checked for the interference of the data. The same procedures are repeatedly performed by writing the binary data to each of the storage elements at the remaining addresses other than the address 0. If the memory unit addresses, range from 0 to N, it is necessary to repeat the testing control procedures N.sup.2 times. Thus, if the storage capacity of the memory unit is increased, a very long testing time is required.
For recent microminiaturized memory units with high access speed, the noise due to high speed switching becomes not negligible, and the convergence time from the initial level to the final level at which the undershoot or overshoot converges is relatively great for the high access speed of the memory units. It is desirable to provide a testing method by which all the storage elements of a memory unit are efficiently tested with the testing time as short as possible.
In the meantime, the proposed methods described above are a normal mode testing procedure for detecting a failure in the storage elements of a memory unit. It should be noted that it is necessary to provide an efficient memory unit testing method of a different mode for detecting a failure in the bit lines of a memory unit. In order to efficiently and accurately test a memory unit, it is desirable to detect not only a failure in the storage elements of the memory unit but also a failure in the bit lines of the memory unit. If one of the bit lines of the memory unit fails, the access time becomes excessively great when power is applied to and cut off from the storage elements connected to the bit line.
FIG. 5 shows a pattern of bit lines within one of a plurality of blocks of a memory unit. In the block B0 of the memory unit in FIG. 5, a set of storage elements, arranged on the same column line, and a sense amplifier SO of the block B0 are interconnected by a pair of bit lines. Also, the other sets of storage elements, arranged on the other column lines, and the sense amplifier S0 are interconnected by the other bit lines. The sense amplifier of each block and the storage elements connected to the same bit line within the block are interconnected by a pair of bit lines. The sense amplifier SO can detect whether the binary data read from one of the storage elements is equal to "0" or "1", based on whether one of the measurements of the sense amplifier from the bit lines is lower or higher than the other one.
The time of the data transmission from one of the storage elements within one block to the sense amplifier via the bit lines is the greatest when the storage element at the first row (farthest from the sense amplifier) is accessed, and is the smallest when the storage element at the final row (nearest to the sense amplifier) is accessed. Thus, the testing procedure in which only the first-row storage elements and the final-row storage elements in each block of a memory unit are accessed is a very efficient method for detecting a failure in the bit lines of the memory unit.
The block B0 of the memory unit is connected to an equalizing unit (not shown in FIG. 5) via an equalizing line which is located above the first row line. In order to perform a high-speed reading, the bit lines BIT1 and BIT2 are short-circuited. Thus, the time for the high-speed reading is the greatest when the final-row storage element (farthest from the equalizing unit) is accessed, and is the smallest when the first-row storage element (nearest to the equalizing unit) is accessed. Therefore, from this point of view, the testing procedure in which only the first-row storage elements and the final-row storage elements in each block of a memory unit are accessed is a very efficient method for detecting a failure in the bit lines of the memory unit.
As the above mentioned points are not taken into consideration in the proposed methods previously described, the proposed methods are not efficient in detecting a failure in the bit lines of the memory unit. If one of the proposed methods is performed to test a memory unit, a great amount of time is required to complete the normal mode testing procedure. The efficiency and accuracy of detecting a failure in the storage elements and bit lines are insufficient for the recent memory units with high access speed. Also, if a failure in the memory unit is detected by performing one of the proposed methods, it is difficult to detect whether the failure is caused by a storage element or a bit line.